DEEP DIVE Intel's Xeon 7 platform, better known by its codename Diamond Rapids, was supposed to launch this year with up to 192 cores backed by a whopping 16 memory channels.
But that's not going to happen. This being Intel, the launch was, to no one's great surprise, delayed until 2027 to give what remains of the company's engineering team time to cut and polish the chip — and polish they certainly have.
At the Hot Chips show this week, Intel revealed the chip won't ship with 192 cores after all — but hold your disappointment because Chipzilla's flagship SKU will actually cram 256 performance cores into a single socket.
In fact, spec-for-spec, the platform is surprisingly well positioned to compete with AMD's sixth-gen Venice Epycs, which will also top out at 256 cores. Well, at least on the high end it will.
As we reported earlier this year, Diamond Rapids won't be a mainstream part. It lacks hyperthreading — what the rest of the industry calls simultaneous multithreading — entirely and it can only be offered in high-core-count SKUs aimed at HPC applications.
There will be no eight channel Diamond Rapids-SP parts. Those got canned earlier this year, which leaves us with just the high-end AP variants. These always are the cooler of the two anyway, but they're not what enterprises have historically bought.
What this means is Diamond Rapids — which for the sake of brevity we're going to refer to as DMR from here on out — won't compete with AMD in every regime, just the very top end.
Intel's next chip, known as Coral Rapids, will see the return of hyperthreading and presumably the next round of SP processors, but we wouldn't write off DMR just yet.
The chip is without a doubt Intel's most sophisticated Xeon ever built. In many ways it feels a bit like Intel's Rome moment. As you may recall, AMD's Epyc Rome saw the House of Zen embrace a truly modular chiplet architecture that disaggregated compute from I/O and memory, and could be added, removed, and reused depending on the kind of CPU it was trying to make.
After faffing about for three generations trying to make chiplets work for them, Intel appears to have found the right glue to stitch everything together and is now having its own Rome moment.
DMR's resemblance to Rome is hard to miss, but the resemblance is only skin deep. Intel really is using a different kind of glue to build its chips.
The chip comprises up to 22 chiplets, which can be added or subtracted depending on the ratio of compute, cache, and memory Intel needs — just like AMD has been doing for the past seven years.
Those chiplets can be broken into three core groups. There are up to 16 core compute dies built on Intel's bleeding-edge 18A-P process tech, four compute building block (CBB) base dies fabbed on Intel 3-T, and two fabric hub dies built on Intel 3 that tie everything together.
We've discussed 18A-P in the past so we won't rehash too much here, but it's a refined version of the 2 nm-class process tech Intel started churning out earlier this year with its Panther Lake mobile processors.
Intel claims the tech delivers the same performance at 18 percent less power, or up to 9 percent higher performance at the same power, and that's before taking into account microarchitectural improvements from DMR's all new performance cores.
